八路彩灯控制器的设计大神们帮帮忙

Question

设计要求： 1．有八只LED，L0……L7 2．显示顺序如下表 3．显示间隔为0.25S，0.5S，1S，2S可调。 序号L0 L1 L2 L3 L4 L5 L6 L7 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 2 1 0 1 1 1 1 1 1 3 1 1 0 1 1 1 1 1 4 1 1 1 0 1 1 1 1 5 1 1 1 1 0 1 1 1 6 1 1 1 1 1 0 1 1 7 1 1 1 1 1 1 0 1 8 1 1 1 1 1 1 1 0 9 1 1 1 1 1 1 1 1 10 0 1 1 1 1 1 1 1 11 0 0 1 1 1 1 1 1 12 0 0 0 1 1 1 1 1 13 0 0 0 0 1 1 1 1 14 0 0 0 0 0 1 1 1 15 0 0 0 0 0 0 1 1 16 0 0 0 0 0 0 0 1 17 0 0 0 0 0 0 0 0 18 1 0 0 0 0 0 0 0 19 1 1 0 0 0 0 0 0 20 1 1 1 0 0 0 0 0 21 1 1 1 1 0 0 0 0 22 1 1 1 1 1 0 0 0 23 1 1 1 1 1 1 0 0 24 1 1 1 1 1 1 1 0 25 1 0 0 0 0 0 0 0 26 0 1 0 0 0 0 0 0 27 0 0 1 0 0 0 0 0 28 0 0 0 1 0 0 0 0 29 0 0 0 0 1 0 0 0 30 0 0 0 0 0 1 0 0 31 0 0 0 0 0 0 1 0 32 0 0 0 0 0 0 0 1 问题补充：要有设计程序 仿真图 可以编译成功的 先谢谢各位高手了 也可以发到我的邮箱 [email protected]

Answer 1

你试试这个行不行： module LED(L_out,clk,resetn,contr); input clk,resetn; input [1:0]contr; output[7:0] L_out; reg[7:0] L_reg; wire clk_gen; reg [2:0] count; reg clk1,clk2,clk3; reg [4:0] state,nextstate; parameter[4:0] idle =5'b00001, stateA=5'b00010, stateB=5'b00100, stateC=5'b01000, stateD=5'b10000; assign L_out=L_reg; always@(posedge clk or negedge resetn) if (resetn==0) begin count<=3'b0;clk1<=0;clk2<=0;clk3<=0; end else if(count==3'b111) count<=0; else count<=count+1; always@(count) begin if (count==3'b001||count==3'b011||count==3'b101||count==3'b111) clk1=~clk1; if (count==3'b011||count==3'b111) clk2=~clk2; if (count==3'b111) clk3=~clk3; end /****** always@(contr) case (contr) case(contr) 2'b00: clk_gen=clk; 2'b01: clk_gen=clk1; 2'b10: clk_gen=clk2; 2'b11: clk_gen=clk3; endcase *******/ assign clk_gen=(contr==0)?clk:(contr==1)?clk1:(contr==2)?clk2:(contr==3)?clk3:1'bx; always@(negedge clk or negedge resetn) if (resetn==1'b0) begin state<=idle; nextstate<=0;L_reg<=8'b1111_1110;end else state<=nextstate; always@(posedge clk_gen) case (state) idle : begin L_reg<=8'b0111_1111;nextstate<=stateA; end stateA: begin if(L_reg!=8'b1111_1110) L_reg<={1'b1,L_reg[7:1]}; else L_reg<=8'b1111_1111; end stateB: begin if(L_reg!=8'b0000_0001) L_reg<={1'b0,L_reg[7:1]}; else L_reg<=8'b0000_0000; end stateC: begin if(L_reg!=8'b1111_1110) L_reg<={1'b1,L_reg[7:1]}; else L_reg<=8'b1000_0000; end stateD: begin if(L_reg!=8'b0000_0001) L_reg<={1'b0,L_reg[7:1]}; else L_reg<=8'b0111_1111; end endcase always @( L_reg)begin case (L_reg) 8'b1111_1110: if(state==stateA) nextstate=stateB; else if(state==stateC) nextstate=stateD; 8'b0000_0001: if(state==stateB) nextstate=stateC; else if(state==stateD) nextstate=stateA; default : nextstate=state; endcase end endmodule本回答被提问者采纳