1. 本文中我们定义了GSML语言作为织女星数字图书馆中新型资源的载体。
Furthermore, we design and implement GSML as the medium of resources in digital library instances.
2. 详细说明：用VHDL语言编写的带有闹钟功能的数字时钟，可实现定时定点闹钟。
Written in VHDL, digital clock with alarm function can be realized fixed-point alarm regularly.
3. 标识符是语言的基本元素，比如单词、数字、化学元素等。
Tokens are the basic elements of the language, such as words, numbers, and chemical elements.
4. 在此基础上，采用了适于实时数据采集与处理的TMS320F2812数字信号处理器，来实现对弹体滚转姿态的采集与传输；并在上位机上使用Visual Basic为开发语言，用于实现数据的接收和处理。
Based on that model, the data acquisition and transmission of the shell bodys roll attitude is implemented by using DSP (TMS320F2812) suitable for real-time data acquisition and processing. And the data reception and data processing is realized by upper PC software which is developed by visual basic.
5. 数字信号处理的各种算法的c语言代码实现。
Digital signal processing algorithms in C language code to achieve.
6. 并根据所得的有关公式，用BASIC语言编制了根据设计要求用计算机设计Butterworh低通数字滤波器并能算出其频响特性的程序。
A program for the design of Butterworth low-pass digital filter based on the requirement of the application has been given with BASIC language.
7. 第一个字符是字母，其余字符，是字母或数字它几乎等价于Python语言中合法的标识符
W* Alphabetic first character, additional characters can be alphanumeric almost equivalent to the set of valid Python identifiers
8. 针对目标自主定位的环境复杂性和高速处理数据的要求，文中用VHDL语言设计了一种基于扩频通信原理的数字相关器。
To satisfy the high speed data processing requirement of automatic orientation in complex environment, based on the spread spectrum communication system, a digital correlator by VHDL is presented.
9. 此文件是用汇编语言编写的数字钟原程序，它包括时钟显示、整点报时和闹钟部分。
This document is a compilation of language digital clock original program, which includes clock, the whole point timer and alarm clock parts.
10. 在此基础上推导了数字PID控制算法，并采用状态机的设计方法实现该控制器的设计，应用VHDL硬件语言进行编程。
Based on which a digital PID control algorithm was deduced, and state machine method was used to finish the design of controller.
11. 为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能，在Xilinx ISE10.1开发平台中，采用Verilog HDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构，并在ModelSim仿真验证平台中仿真了实现设计。
In order to research different implementations of FIR digital filter with FPGA on their resource consuming as well as the speed performance, the improved serial structure, parallel structure and DA structure of FIR digital filter were respec-tively implemented with Verilog HDL on the Xilinx ISE10.1development platform, and then simulated on the Modelsim sim-ulation platform.
12. 求职意向工作性质：全职目标职能：软件测试教育经历 2001/09--2005/07 河北工程大学电气工程及其自动化专业本科主修课程：模拟电子，数字电子，计算机组成原理，单片机原理与应用技术，C语言程序设计，VB程序设计证书 2005/04 大学英语六级 2004/10 全国计算机等级三级网络
Job orientation Type of job: Full time sort of work: software testing Educational background Graduated from Heibei university of Engineering in the field of Electrical Engineering and Automation Majors: analog electronics, digital electronics, computer architecture, and application of principles of SCM technology, C language programming.
13. 求职意向工作性质：全职目标职能：软件测试教育经历 2001/09--2005/07 河北工程大学电气工程及其自动化专业本科主修课程：模拟电子，数字电子，计算机组成原理，单片机原理与应用技术，C语言程序设计，VB程序设计证书 2005/04 大学英语六级 2004/10 全国计算机等级三级网络
Seek job an intention Work property: Full-time Target working talent: Software test Educate career 2001/09-2005/07 rivers north electrical engineering of the engineering university and the professional undergraduate course of its automation Major in a course:Imitate an electronics, numerical electronics, the calculator constitutes principle, single slice machine principle and application technique, C language program design, VB program design Certificate 2005/04 university Englishs six classes 2004/10 national x-rated network of the calculator grades
14. 在较小的国家，语言或文化社区，这个数字将是不太可能获得更广泛名人。
In a smaller country, linguistic or cultural community, a figure will be less likely to gain a broader celebrity.
15. 使用SOPC Builder软件生成Nios II软核，将CPU、运算器、存储器、定时器等成熟的IP核应用到盐度计设计中，同时使用硬件描述语言VHDL将底层驱动逻辑设计为用户IP核，如激励源IP核、高灵敏度数字检流计IP核、模拟测温IP核、日历时钟IP核、数字测温IP核、键盘IP核、液晶显示IP核等。
We design hardware logic for salinometer with Quartus II software, and use SOPC Builder to design Nios II, CPU、arithmetical unit、MEMORY、TIMER and other mature IP core are apply to salinometer. We use the hardware description language VHDL to design bottom drives, and make them as customer IP core, such as excitation source IP core、high sensitive digital galvanometer IP core、analog temperature measurement IP core、digital temperature measurement IP core、calendar and time IP core、keyboard IP core、LCD IP core.
16. 语法编辑器是一个可以对程序设计语言进行语法编辑的文本编辑器，它对程序设计语言进行语法关键字进行加亮处理，如注释行、字符串、语法关键字、数字等，这样使得源程序更容易阅读，VB、VC++、DELPHI 等开发环境都提供了语法编辑功能，相信开发人员都会有切身的体会。
Syntax editor of a right programming language syntax editor for the text editor, its programming language syntax highlighting keywords, such as Notes OK, string, grammar keywords, figures such that the source code makes it easier to read, VB, VC, development environments such as Delphi has given a grammar editing function, I believe developers will have personal experiences.
17. C语言开发的数字钟程序，希望对大家有用！
Development of the C language digital clock procedures in the hope that it may be useful right!
18. 介绍了在一片EPF 10K 10LC 84-4芯片内用VHDL语言编程实现了步进电机十六细分控制器的PWM模块、速度控制模块、数字比较模块等功能，该系统无需外接D/A转换器，结构简单，控制精度高，具有广泛的应用前景。
It was introduced that in a piece of EPF10K10LC84-4 chip, the stepping motor sixteen subdivision controllers about the PWM module, the speed control module, digital comparison module and so on have been achieved with VHDL language programming. The system need not link...
19. 硬件描述语言是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
20. 硬件描述语言是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
VHDL is considered as a core of digital system design and a key technique of imptement digital systems design.
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